Cache-Timing Attack Against HQC

Authors

  • Senyang Huang Lund University, Lund, Sweden
  • Rui Qi Sim The University of Adelaide, Adelaide, Australia
  • Chitchanok Chuengsatiansup The University of Melbourne, Melbourne, Australia
  • Qian Guo Lund University, Lund, Sweden
  • Thomas Johansson Lund University, Lund, Sweden

DOI:

https://doi.org/10.46586/tches.v2023.i3.136-163

Keywords:

Side-channel attacks, Code-based cryptography, NIST PQC standardization, HQC

Abstract

In this paper, we present the first chosen-ciphertext (CC) cache-timing attacks on the reference implementation of HQC. We build a cache-timing based distinguisher for implementing a plaintext-checking (PC) oracle. The PC oracle uses side-channel information to check if a given ciphertext decrypts to a given message. This is done by identifying a vulnerability during the generating process of two vectors in the reference implementation of HQC. We also propose a new method of using PC oracles for chosen-ciphertext side-channel attacks against HQC, which may have independent interest.
We show a general proof-of-concept attack, where we use the Flush+Reload technique and also derive, in more detail, a practical attack on an HQC execution on Intel SGX, where the Prime+Probe technique is used. We show the exact path to do key recovery by explaining the detailed steps, using the PC oracle. In both scenarios, the new attack requires 53, 857 traces on average with much fewer PC oracle calls than the timing attack of Guo et al. CHES 2022 on an HQC implementation.

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Published

2023-06-09

Issue

Section

Articles

How to Cite

Cache-Timing Attack Against HQC. (2023). IACR Transactions on Cryptographic Hardware and Embedded Systems, 2023(3), 136-163. https://doi.org/10.46586/tches.v2023.i3.136-163