RISC-V Instruction Set Extensions for Lightweight Symmetric Cryptography
DOI:
https://doi.org/10.46586/tches.v2023.i1.193-237Keywords:
ISA, ISE, lightweight cryptographyAbstract
The NIST LightWeight Cryptography (LWC) selection process aims to standardise cryptographic functionality which is suitable for resource-constrained devices. Since the outcome is likely to have significant, long-lived impact, careful evaluation of each submission with respect to metrics explicitly outlined in the call is imperative. Beyond the robustness of submissions against cryptanalytic attack, metrics related to their implementation (e.g., execution latency and memory footprint) form an important example. Aiming to provide evidence allowing richer evaluation with respect to such metrics, this paper presents the design, implementation, and evaluation of one separate Instruction Set Extension (ISE) for each of the 10 LWC final round submissions, namely Ascon, Elephant, GIFT-COFB, Grain-128AEADv2, ISAP, PHOTON-Beetle, Romulus, Sparkle, TinyJAMBU, and Xoodyak; although we base the work on use of RISC-V, we argue that it provides more general insight.
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Copyright (c) 2022 Hao Cheng, Johann Großschädl, Ben Marshall, Dan Page, Thinh Pham
This work is licensed under a Creative Commons Attribution 4.0 International License.